1. Field of the Invention
The present invention relates to a microprocessor system and, more particularly, to a microprocessor system having a multiplexed address/data bus which is provided with a plurality of output TTL gates.
2. Description of the Prior Art
Several microprocessors may present a multiplexed address/data bus to reduce the total number of external connecting pins. During an external operation performed by such microprocessors (for example, a memory access or an input/output operation) both addresses and data are present, during different times of the machine cycle, on the channel or multiplexed bus. The selection between the two kinds of information is performed by the use of suitable control signals supplied by the microprocessors. The only restraint for using a microprocessor with a multiplexed bus is the demultiplexing process of the bus in order to enable it to interface with standard memory circuits. Demultiplexing is generally accomplished by means of a register which latches the information representative of an address in response to a suitable microprocessor control signal--at a predetermined latching time of the cycle. During the remainder of the machine cycle the address/data bus changes to a data bus. Microprocessors, that are implemented with MOS (Metal-Oxide-Semiconductor) technology, provide a limited capacity of static load (fan out) to their own bus lines. The output logic gate coupled to each of said lines can, in fact, output only a small amount of current. If the line is overcharged it can be damaged by overheating and it may work incorrectly. (Most of the microprocessor manufacturers point out the maximum static load of the bus lines.) Typical static load features consists of a single TTL load. Generally such load features can be absorbed for microprocessor systems implemented on a single plate where the microprocessor is directly interconnected through the data bus and the address bus to memories and peripherals of its own MOS family. However, in systems where the microprocessor has to drive several TTL inputs the fan-out of the microprocessor bus lines must be increased by the insertion of additional drivers between bus lines and TTL loads. The present invention avoids the insertion of any drivers on a data bus of this type.